Effective Camera Architecture Design (cont.)
Lack of understanding about basic architectural limitations
Some sensors contain image processing ICs which can offload
even more processes from the main control CPU. Not surprisingly, these
will be more expensive than their dumber bretheren,
so on-board Bayer and JPEG processing- as well as image
correction, will have to be done by the processor controlling the
camera
and not by the sensor module. In this instance, having the proper CPU
control paths and horsepower to do the job is essential.
Shown below are two architectures: the simplist one is using a single sensor module with internal image processor, and the next one is shown accomplishing the same thing using discrete circuitry. Obviously the one with discrete circuitry is more complicated and costly, but has the flexibility and the power to accomplish some unique problems that the single sensor approach cannot.
The single sensor system (above) is the easiest to implement, but there are hidden tradeoffs and limitations. This architecture requires an image processing core to demosaic and convert data to an image format prior to transfering to the host. Second, the CPU must be capable of supporting the voltage levels that the sensor produces, so both devices must be run at the same rail voltage. If not, the CPU must at least have a bank select voltage that is common to the sensor's I/O- which may be uncommon. Third, the CPU must support either a legacy parallel interface, or the new CSI-2 interface (LVDS) - which pushes up the cost of this component. Processors that do support direct sensor input will often have internal image processing DSPs that lower the system cost by allowing the use of simple 'Dumb' sensors in this configuration. If they don't, the sensor module must contain the processing chip which raises the cost of this item. Despite the tradeoffs, this is the optimum solution for most applications.
The Multiple sensor design above may or may not have smart sensors attached. FPGA vendors now produce IP that can really help engineers in the design process. SDRAM controllers, Bayer and JPEG image processing cores, and built-in multiplexers can simplify chip count while providing a powerful but small system. As the number of sensors go up though, the cost and size of the FPGA increases. Still, the number of overall discretes may remain constant, and the system can be designed into a very tiny space. The other advantage here is that the CPU doesn't have to do much except setup, making it a very low cost device. In that case, the arrow shown 'To host...' may be attached directly from the FPGA, and DMA may be accomplished in tens, if not hundreds of Megabytes per second depending on the image link chosen.
Looking at the sensor specs. reveals much about the electrical operation of the devices, but...
Not planning for post-image capture processing.
(to be continued)